1. Field
Various features relate to integrated circuits, and more specifically, to integrated circuit (IC) identification (ID) and IC dependability verification using ring oscillator based physical unclonable function and age detection circuitry.
2. Background
In the era of pervasive computing a lot of security issues exist related to software copyright protection, counterfeit ICs (i.e., chips), and system reliability. Software protection is a family of computer security techniques that are used to prevent the unauthorized copying of software. In other words, software must be able to determine whether the user is properly licensed to use it, and run only if this is the case. Another problem related to software protection is how to identify whether the chip or platform, on which the software is running, is a counterfeit chip. Counterfeit chips have proliferated throughout the industry and are a risk to the electronics supply chain. Consequently, identifying and restricting the usage of counterfeit chips in the electronics supply chain is vital.
An on-chip Physical Unclonable Function (PUF) is a chip-unique challenge-response mechanism exploiting manufacturing process variations inside ICs. The relationship between a challenge and the corresponding response is determined by complex, statistical variations in logic and interconnects in the IC. Different PUF implementations in ICs may be found in the prior art. For example, a ring-oscillator based PUF exploits manufacturing process variations of the IC that cause random but static variations in the frequency of identically laid-out ring oscillators.
FIG. 1 illustrates a schematic block diagram of one example of a ring oscillator based PUF circuit 102 found in the prior art. A plurality of ring oscillators (ROs) 104 may be concurrently enabled and their outputs are sent to two or more switches (multiplexers) 106, 108. A challenge serves as an input to the switches 106, 108 which causes each switch 106, 108 to then select a single RO from among the plurality of ROs 104. The challenge sent to the switches 106, 108 is designed such that each switch 106, 108 selects a different RO. The selected ROs each have a slightly different resonating frequency associated with them due to slight manufacturing variations at the semiconductor level even though each may have been manufactured in an attempt to make them identical. The PUF output response is generated by a pair-wise comparison 114 of these selected ring oscillators' frequencies as measured/stored by the counters 110 and 112. For example, if the first counter 110 detects a higher frequency than the second counter 112, then a logical “1” may be generated, otherwise a logical “0” may be generated. In this fashion the comparisons made represent a challenge/response mechanism, where the chosen RO pair is the challenge and the RO frequency comparison result is the response.
Ideally, each RO pair selected as a challenge will generate a unique response. The response generated should not be able to be determined ahead of time based on the challenge input. Moreover, the same challenge input into the PUF should generate the same response output every time. However, among other things, over time and use one or more of these properties may not hold true. For example, over time one RO's frequency may slow down due to overuse and the same challenge input may generate a different response output (e.g., a logical “1” may flip to a “0”).
An RO-based PUF circuit like the one described above may be used to generate a chip identifier number. However, a chip identification security system that merely relies on a chip identifier number generated merely in this way is inherently limited.
As CMOS process technology continues to follow an aggressive scaling roadmap, designing reliable circuits has become ever more challenging with each technological milestone. Reliability issues such as bias temperature instability (BTI), hot carrier injection (HCI), and time-dependent dielectric breakdown (TDDB) have become more prevalent as the electrical field continues to increase in nano-scale CMOS devices. One of the most pressing of these challenges is negative bias temperature instability (NBTI) caused by the trap generation in the Si—SiO interface of PMOS transistors. Consequently, precise measurement of digital circuit degradation is a key aspect of designing aging-tolerant circuits.
FIG. 2 illustrates a schematic block diagram of an IC age sensor circuit 200 found in the prior art. Two RO 202, 204 outputs are coupled to a phase comparator 206 that determines the frequency difference fdiff between the ROs 202, 204. The first RO 202 (e.g., ROSTR) is “stressed” because it is almost always powered ON (i.e., it is continuously operating) with a supply voltage level VDD-STR, which is greater than the nominal supply voltage VDD of the chip. By contrast, the second RO 204 (e.g., ROREF) is typically powered OFF (i.e., it is not operational). Then, during times where a measurement is desired, both ROs are rendered operational (i.e., turned ON) at the nominal supply voltage VDD and the frequency difference between the ROs 202, 204 is measured by the phase comparator 206. Over time, the stressed RO's 202 operational frequency will decrease relative to the unstressed RO's 204 operational frequency (i.e., fdiff will increase). The age of the IC age sensor circuit 200, and thus in turn the age of a larger circuit on which the sensor circuit 200 resides, may then be determined by analyzing the amount by which fdiff increases over time.
Each of the circuits described above occupy precious chip area on the active surface of an IC. Thus, an improved circuit design that can extract the benefits afforded by PUF security circuits and IC age sensor circuits with a reduction in chip area needed to implement such systems is valuable. Moreover, there is always a need for increased capabilities of a system to identify counterfeit chips and perform chip health monitoring (i.e., detect chip aging).